In virtually all modern data processing systems, the execution of various operations such as arithmetic operations, logical operations and even data transfer operations, may result in the generation of several bits of data to indicate the outcome status of instruction execution. These bits are typically referred to as condition codes. As a simple example, a special condition code setting may be set after an arithmetic addition which results in an overflow due to the addends being too large for the number of bits available for the result. The use of condition codes permeates the execution of almost every instruction.
A classic example of an instruction which produces condition code changes upon execution is the compare instruction which sets a condition code to “zero” if the operands are equal, to “one” if the first operand is strictly less than the second operand and to “two” if the first operand is strictly greater than the second operand. The compare instruction represents an archetypical use of condition code settings.
For a number of reasons, it may be desirable to emulate the instructions designed for one computer architecture on another system with a different set of executable instructions. For example, emulation may be employed in system design or test. It may also be employed to expand the capabilities of one data processing system so that it is enabled to handle instructions written for another system. The present invention relates to the handling of condition code settings in the context of instruction emulation. While the systems and methods of the present invention are widely applicable to any emulation method where condition codes are present, it is particularly applicable to the emulation of the z/Architecture. However, the principles set forth herein are applicable to any source architecture and to any target architecture.
In the principle emulation environment considered in the present description, it is the job of emulation software to accept, as input, strings of source architecture instructions and to generate therefrom strings of instructions that, when run on the target architecture, produce the same results. These results include the setting of various condition codes, such as sign, carry, overflow and various others indicating exceptions and machine states. It is noted that while an emulation environment preferably results in the setting of hardware or condition code elements in the target architecture, the present invention also contemplates the situation in which condition codes are generated and stored in locations other than condition code registers in the target machine.
It is to be particularly noted that the present invention, deliberately avoids the conventional handling of condition code generation. An example of this difference is provided through a brief consideration of the compare instruction. This instruction compares two operands and sets a two bit condition code according to the outcome of the comparison. For example, if the comparison of the two operands determines that they are the same, the condition code is set to zero. If it is determined that the first operand is strictly less than the second operand the condition code is set to one. Lastly, if it is determined that the first operand is greater than the second operand, the condition code is set to two. In conventional approaches to the emulation of a compare instruction, the result is the construction of a sequence of instructions, which include three branch instructions. For the reasons set forth immediately below the presence of branch instructions in the target architecture instruction stream is undesirable.
Branch instructions are undesirable for at least two reasons. In particular, it is noted that most modern data processing architectures include features known as branch prediction. In these architectures, a guess is made as to which of two or more paths that the instruction stream will follow after encountering a branch instruction. If a correct guess is made, then all is well and machine processing time is thereby speeded up. However, if an incorrect to guess is made the machine hardware must backtrack through the path taken, and then take another path. At this point in time, the branch instruction is seen to be a detriment to overall processing speed. Accordingly, it is seen that branch instructions introduce complications which are not otherwise present. Furthermore, as a second reason for their avoidance, is noted that branch instructions actually consume the aforementioned branch prediction resources so that they are thus not available for other instruction streams being executed by a processor. Thus branch instructions are not only potentially wasteful in and of themselves, they also deprive other instruction streams of limited, yet valuable, computer resources.
Accordingly, it is seen that the designer of emulation systems is faced with the paradoxical choice of needing branch instructions to successfully emulate the generation of condition code settings in target architectures while at the same time desiring to avoid branching instructions because of their disadvantages. This problem is especially severe when condition code generation and functionality in the target architecture are quite different from that found in the architecture of the source machine.
It is to be particularly noted that computer programs that emulate the machine state of the z/Architecture deal with many z/Architecture instructions that modify the condition codes. In short, the z/Architecture is a prime exemplar of an architecture in which condition code settings are typically quite different than that found in other architectures, especially ones that have historically grown up from relatively simple microprocessor designs. Additionally, the modification of condition code settings in the z/Architecture is pervasive. The generation and use of condition code settings is most typically found as the result of performing an arithmetic, logical or compare operations after which one or more condition code settings are changed based on the result or other factors. The pervasiveness of condition code modifying instructions in the z/Architecture and the sometimes arbitrary semantics of these instructions introduces complicated control flow to the stream of instructions that are ultimately executed on the target architecture. This control flow adds considerable space and performance overhead to the emulated instructions. The present invention is directed to more efficiently handling this situation. While the method and system herein are particularly applicable to the so-called z/Architecture which is present in large data processing systems manufactured and sold by the assignee of the present invention, it is by no means limited to that architecture as a base of supply for source instructions.
It should also be noted that the present invention is employed in two contexts or modes. In one mode, source computer instructions are converted into target machine instructions for later execution. In another mode of operation, more akin to the operation of interpreters, source instructions are converted into target instructions for immediate execution. The present invention, in its broadest scope, contemplates both of these modalities of operation.